A 1.2V, 30MIPS, 0.3mA / MIPS and 200 MIPS, 0.58mA / MIPS Digital Signal Processors (Special Issue on Low-Power High-Speed CMOS LSI Technologies)

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概要

• 論文の詳細を見る

• High-speed and low-power DSPs have been developed for versatile applications, especially for digital communications. These DSPs contain a 16-bit fixed point DSP core with multiple buses, highly tuned instruction set and low-power architecture, featuring 0.45mA / MIPS, 100-120 MIPS performance by a single CPU core, 200 MIPS performance by dual CPU core architecture, respectively and also contain a 1.2V low-voltage DSP core with 30 MIPS performance for super low-power applications. In this paper, new architecture VIA2 programming ROM for high-speed and new D flip-flop circuit considering the impact of pocket implantation process for low power are discussed, including key C-MOS process technology.

• 社団法人電子情報通信学会の論文
• 2000-02-25

著者

• Mizushima Shintaro

  Texas Instruments Japan Limited Dsp Development Japan Asp Worldwide Development

• TAKAHASHI Hiroshi

  Texas Instruments Japan Limited DSP Development Japan, ASP Worldwide Development

• Takahashi Hiroshi

  Texas Instruments Japan Limited Dsp Development Japan Asp Worldwide Development

関連論文

• A 1.2V, 30MIPS, 0.3mA / MIPS and 200 MIPS, 0.58mA / MIPS Digital Signal Processors (Special Issue on Low-Power High-Speed CMOS LSI Technologies)

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