Design Considerations of Data-Driven Self-Timed RSFQ Adder Circuits(Special Issue on Superconductive Electron Devices and Their Applications)

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概要

• 論文の詳細を見る

• We have designed rapid single-flux-quantum (RSFQ) adder circuits using two different architectures: one is the conventional architecture employing globally synchronous clocking and the other is the data-driven self-timed (DDST) architecture. It has been pointed out that the timing margin of the RSFQ logic is very sensitive to the circuit parameter variations which are induced by the fabrication process and the device parameter uncertainty. Considering the physical timing in the circuits, we have shown that the DDST architecture is advantageous for realizing RSFQ circuits operating at very high frequencies. We have also calcualted the theoretical circuit yield of the DDST adders and shown that a four-bit system operating at 10GHz is feasible with sufficient operating margin, considering the present 1kA/cm^2 Nb Josephson technology.

• 社団法人電子情報通信学会の論文
• 1998-10-25

著者

• Yoshikawa Nobuyuki

  The Faculty Of Engineering Yokohama National University

• TAGO Hiroshi

  the Faculty of Engineering, Yokohama National University

• YONEYAMA Kaoru

  the Faculty of Engineering, Yokohama National University

• Tago H

  Yokohama National Univ. Yokohama Jpn

• Yoneyama K

  Yokohama National Univ. Yokohama‐shi Jpn

関連論文

• Design Considerations of Data-Driven Self-Timed RSFQ Adder Circuits(Special Issue on Superconductive Electron Devices and Their Applications)

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