Self-Learning Analog Neural Network LSI with High-Resolution Non-Volatile Analog Memory and a Partially-Serial Weight-Update Architecture (Special Issue on New Concept Device and Novel Architecture LSIs)

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概要

• 論文の詳細を見る

• A self-learning analog neural network LSI with non-volatile analog memory which can be updated with more than 13-bit resolution has been designed, fabricated and tested for the first time. The non-volatile memory is attained by a new floating-gate MOSFET device that has a charge injection part and an accumulation part separated by a high resistance. We also propose a partially-serial weight-update architecture in which the plural synapse circuits use a weight-update circuit in common to reduce the circuit area. A prototype chip fabricated using a 1.3-μm double-poly CMOS process includes 50 synapse elements and its computational power is 10 MCPS. The weights can be updated at a rate of up to 40 kHz. This chip can be used to implement backpropagation networks, deterministic Boltzmann machines, and Hopfield networks with Hebbian learning.

• 社団法人電子情報通信学会の論文
• 1997-07-25

著者

• Morie T

  Ntt Network Service Systems Laboratories

• MORIE Takashi

  NTT Network Service Systems Laboratories

• FUJITA Osamu

  NTT Electronics Technology Corporation

• UCHIMURA Kuniharu

  NTT System Electronics Laboratories

• Fujita O

  Ntt Electronics Technology Corporation

• Fujita Osamu

  Ntt Electronics Technology

関連論文

• Self-Learning Analog Neural Network LSI with High-Resolution Non-Volatile Analog Memory and a Partially-Serial Weight-Update Architecture (Special Issue on New Concept Device and Novel Architecture LSIs)
• A Sparse Memory Access Architecture for Digital Neural Network LSIs (Special Issue on New Concept Device and Novel Architecture LSIs)

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