A 65 ns 3 V-only NAND-Flash Memory with New Verify Scheme and Folded Bit-Line Architecture

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概要

• 論文の詳細を見る

• An experimental 3 V-only 4 Mb NAND Flash memory with 65 ns access time has been developed using a new charge pump circuit and novel circuit techniques such as folded bit-line architecture. By adopting a new program verify technique, programming time is reduced to 11μs/Byte.

• 一般社団法人電子情報通信学会の論文
• 1995-07-25

著者

• Arakawa Hideki

  Cell Development Department Sony Corporation

• Satori Kenichi

  Cell Development Department Sony Corporation

• Nobukata Hiromi

  Cell Development Department, Sony Corporation

• Hiramatsu Shinji

  Cell Development Department, Sony Corporation

• Nobukata Hiromi

  Cell Development Department Sony Corporation

• Hiramatsu Shinji

  Cell Development Department Sony Corporation

関連論文

• A 65 ns 3 V-only NAND-Flash Memory with New Verify Scheme and Folded Bit-Line Architecture

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