Verification of Scalable-Delay-Insensitive Asynchronous Circuits
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概要
- 論文の詳細を見る
The Scalable-Delay-Insensitive (SDI) model is proposed for high-performance asynchronous system design. In this paper, we focus on checking whether a circuit under SDI model satisfies some untimed properties, and formally show that checking these properties in the SDI model can be reduced to checking the same properties in the bounded delay model. This result suggests that the existing verification algorithms for the bounded delay model can be used for the verification of SDI circuits, which significantly helps the designers of SDI circuits.
- 社団法人電子情報通信学会の論文
- 1999-03-25
著者
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YAMAZAKI ATSUSHI
Department of Resources and Environmental Engineering, School of Creative Science and Engineering, W
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Ryu Hiroshi
Department Of Neurosurgery Hamamatsu University School Of Medicine
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Ryu Hiroshi
Department Of Computer Science Tokyo Institute Of Technology:(present) Nec
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Yamazaki A
Tokyo Inst. Technol. Tokyo Jpn
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YONEDA Tomohiro
Department of Computer Science, Tokyo Institute of Technology
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Yamazaki Atsushi
Department Of Biotechnology Biological Resource Center (nbrc) National Institute Of Technology And E
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Yoneda Tomohiro
Department Of Computer Science Tokyo Institute Of Technology
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