Fast Precise Interrupt Handling without Associative Searching in Multiple Out-Of-Order Issue Processors

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概要

• 論文の詳細を見る

• This paper presents a new approach to the precise interrupt handling problem in modern processors with multiple out-of-order issues. It is difficult to implement a precise interrupt scheme in the processors because later instructions may change the process states before their preceding instructions have completed. We propose a fast precise interrupt handling scheme which can recover the precise state in one cycle if an interrupt occurs. In addition, the scheme removes all the associative searching operations which are inevitable in the previous approaches. To deal with the renaming of destination registers, we present a new bank-based register file which is indexed by bank index tables containing the bank identifiers of renamed register entries. Simulation results based on the superscalar MIPS architecture show that the register file with 3 banks is a good trade-off between high performance and low complexity.

• 社団法人電子情報通信学会の論文
• 1999-03-25

著者

• Park In-cheol

  Dept. Of Electrical Engineering And Computer Science Korea Advanced Institute Of Science And Technol

• Park In-cheol

  Dept. Of Electrical Engineering Korea Advanced Institude Of Science And Technology

• Nam Sang-joon

  Dept. Of Electrical Engineering Korea Advanced Institude Of Science And Technology

• KYUN Chong-Min

  Dept. of Electrical Engineering, Korea Advanced Institude of Science and Technology

• Kyun Chong-min

  Dept. Of Electrical Engineering Korea Advanced Institude Of Science And Technology

関連論文

• Fast Precise Interrupt Handling without Associative Searching in Multiple Out-Of-Order Issue Processors
• An Automatic Interface Insertion Scheme for In-System Verification of Algorithm Models in C(Special Section on VLSI Design and CAD Algorithms)

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