Resolving Load Data Dependency Using Tunneling-Load Technique

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概要

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• The new technique for reducing the load latency is presented. This technique, named tunneling-load, utilizes the register specifier buffer in order to reduce the load latency without fetching the data cache speculatively, and thus eliminates the drawback of any load address prediction techniques. As a consequence of the trend toward increasing clock frequency, the internal cache is no longer able to fill the speed gap between the processor and the external memory, and the data cache latency degrades the processor performance. In order to hide this latency, several techniques predicting the load address have been proposed. These techniques carry out the speculative data cache fetching, which causes the explosion of the memory traffic and the pollution of the data cache. The tunneling-load solves these problems. We have evaluated the effects of the tunneling-load, and found that in an in-order-issue superscalar platform the instruction level parallelism is increased by approximately 10%.

• 社団法人電子情報通信学会の論文
• 1998-08-25

著者

• Sato Toshinori

  Microelectronics Engineering Laboratory Toshiba Corporation

関連論文

• Resolving Load Data Dependency Using Tunneling-Load Technique

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