High-Fair Bus Arbiter for Multiprocessors

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概要

• 論文の詳細を見る

• This paper presents a high-fair bus arbiter for general multiprocessor systems. The arbiter realizes a new bus arbitration protocol which is a modification to the priority scheme specified in the group protocol [6] enabling it to operate effectively on shared-bus multiprocessors to achieve fairness. The modified priority scheme not only guarantees that processors with low priority will gain access to the bus without being completely lock out as might happen during heavy traffic, but also assures that both bus waiting time and utilization on average of each processor closely approximate to other's. Hardware structure for the proposed protocol is also presented; the circuit is also capable of the feature of live insertion of processors from the system.

• 社団法人電子情報通信学会の論文
• 1997-01-25

著者

• Lee Chiung-san

  Computer Center National Taipei College Of Nursing

関連論文

• High-Fair Bus Arbiter for Multiprocessors

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