Quad-Processor Redundancy for a RISC-Based Fault Tolerant Computer (Special Issue on Fault-Tolerant Computing)

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概要

• 論文の詳細を見る

• The fault tolerant computer (FTC) is applied as a communication or database server in the information service and computer aided process control fields. User requires of the FTC are to provide the current level of performance and software transparency needing no additional dedicated program for fault tolerance. To meet these requirements, we propose quad-processor redundancy (QPR) architecture that combines dual-RlSC based duplicated CPUs integrating main memories, and duplicated I/O subsystems by using some additional hardware. Duplicated CPUs run under the instruction level synchronization (lock step operation), and the duplicated I/O subsystems are managed by an operating system. When a fault is detected, the faulty CPU is isolated by hardware. User program is continuously executed by the remaining CPU. We applied the QPR to our UNIX servers, and achieved satisfactory levels of performance.

• 1997-01-25

著者

• Yamaguchi Shinichiro

  Hitachi Research Laboratory Hitachi Ltd.

• Miyazaki Yoshihiro

  Omika Works Hitachi Ltd.

• Ishikawa Sakou

  Office Systems Division Hitachi Ltd.

• NAKAMIKAWA Tetsuaki

  Hitachi Research Laboratory, Hitachi Ltd.

• MIYAZAKI Naoto

  Hitachi Research Laboratory, Hitachi Ltd.

• MORITA Yuuichirou

  Hitachi Research Laboratory, Hitachi Ltd.

• Miyazaki N

  Tokyo Inst. Technol. Yokohama‐shi Jpn

• Nakamikawa Tetsuaki

  Hitachi Research Laboratory Hitachi Ltd.

• Morita Yuuichirou

  Hitachi Research Laboratory Hitachi Ltd.

関連論文

• Quad-Processor Redundancy for a RISC-Based Fault Tolerant Computer (Special Issue on Fault-Tolerant Computing)

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