Technology Mapping for FPGAs with Composite Logic Block Architectures (Special Issue on Synthesis and Verification of Hardware Design)

概要

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A new technology mapping algorithm is developed on a general model of FPGA with composite logic block architectures, consisting of different sizes of look-up tables (LUTs) and possibly different logic gates. In additions, the logic blocks may have hard-wired connections and limit accessible fanouts. Xilinx XC4000 is one example containing LUTs of different sizes and ATampT ORCA is another example containing both LUTs and logic gates. We use a multiple-fanout pattern graph library to model the composite logic block and a premapping technique to generate the subject graph dynamically. A new matching algorithm and a new covering algorithm are also developed for the subject graph covering. The experimental results show that our algorithm is an effective technology mapper for FPGAs with composite logic block architectures, especially for larger circuits. Over a set of MCNC benchmarks, our algorithm requires on the average 4.25% fewer CLBs than PPR, 6.79% fewer CLBs than TEMPT, and 2.79% fewer CLBs than ASYL when used as the XC4000 mapper. Over a set of larger benchmarks, our algorithm outperforms PPR by J 3.70%. Very encouraging results were obtained when our algorithm is used as an ORCA mapper, while there was no prior published results.
一般社団法人電子情報通信学会の論文
1996-10-25