The Effect of CMOS VLSI IDDq Measurement on Defect Level

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概要

• 論文の詳細を見る

• In the final stages of VLSI testing, improved quality VLSI testing is an important subject for ensuring reliability in the forwarded VLSI market. On the other hand, developments in high integration technology have resulted in an increased number of functional blocks in VLSI devices and an increased number of gates for each terminal. Consequently, it has become more difficult to improve the quality of VLSI tests. We have developed a new test method in addition to conventional testing methods intended for improving the test coverage in VLSI tests. This new test method analyzes the relationship between IDDq (Quiescent Power Supply Current) of DUT and DUT failure by applying the concept of the toggle rate. Accordingly, in this paper we report that the results of IDDq testing confirm a correlation with defect level.

• 社団法人電子情報通信学会の論文
• 1995-07-25

著者

• Hamada Masanori

  Lsi Development Center Matsushita Electronics Corporation

• Hirase Junichi

  LSI Development Center, Matsushita Electronics Corporation

• Hirase Junichi

  Lsi Development Center Matsushita Electronics Corporation

関連論文

• The Effect of CMOS VLSI IDDq Measurement on Defect Level

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