A Selective Invalidation Strategy for Cache Coherence

概要

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The overall performance of a shared-memory common bus multiprocessor system can be seriously affected by useless coherence-related actions. This occurs, in particular, when a private data block of a process becomes resident in more than one cache as a consequence of the migration of the owner process. We introduce a hardware solution to eliminate these useless shared copies, and show how this technique can be applied to a specific coherence protocol. Two extreme workload conditions are properly selected to evaluate the performance of a multiprocessor system.
社団法人電子情報通信学会の論文
1995-10-25