A Modular Inversion Hardware Algorithm with a Redundant Binary Representation

スポンサーリンク

概要

• 論文の詳細を見る

• A hardware algorithm for modular inversion is proposed. It is based on the extended Euclidean algorithm. All intermediate results are represented in a redundant binary representation with a digit set {0,1,-1}. All addition / subtractions are performed without carry propagation. A modular inversion is carried out in O(n) clock cycles where n is the word length of the modulus. The length of each clock cycle is constant independent of n. A modular inverter based on the algorithm has a regular cellular array structure with a bit slice feature and is very suitable for VLSI implementation. Its amount of hardware is proportional to n.

• 社団法人電子情報通信学会の論文
• 1993-08-25

著者

• Takagi Naofumi

  Faculty Of Engineering Kyoto University

関連論文

• A Modular Inversion Hardware Algorithm with a Redundant Binary Representation

スポンサーリンク