Random Double Bit Error Correcting : Single b-bit Byte Error Correcting(DEC-S_bEC)Codes for Memory Systems

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概要

• 論文の詳細を見る

• Besides single byte errors which are caused by single chip failures, semiconductor memories used in some applications, such as satellite memory systems, are highly vulnerable to randorn double bit, errors. It is therefore necessary to design Double bit Error Correcting-Single b-bit byte Error Correcting(DEC-S_bEC)codes which correct both random double bit errors and single b-bit byte errors. This correspondence proposes a class of generic DEC-S_bEC codes that are applicable to computer memory systems using recent high clensity DRAM chips with wide I/O data, such as, 8, 16 or 32 bits per chip. The proposed DEC-S_8EC codes are suitable for memory systems using DRAM chips with 8-bit I/O data, and require 24 check bits for practical information lengths such as 64 and 128 bits.

• 社団法人電子情報通信学会の論文
• 2002-01-01

著者

• Umanesan G

  Tokyo Inst. Technol. Tokyo Jpn

• UMANESAN Ganesan

  the Graduate School of Information Science and Engineering, Tokyo Institute of Technology

• FUJIWARA Eiji

  the Graduate School of Information Science and Engineering, Tokyo Institute of Technology

• Umanesan Ganesan

  The Graduate School Of Information Science And Engineering Tokyo Institute Of Technology

• Fujiwara Eiji

  The Graduate School Of Information Science And Engineering Tokyo Institute Of Technology

関連論文

• Random Double Bit Error Correcting : Single b-bit Byte Error Correcting(DEC-S_bEC)Codes for Memory Systems
• Burst Error Recovery for VF Arithmetic Coding
• Systematic Binary Deletion/Insertion Error Correcting Codes Capable of Correcting Random Bit Errors
• Metrics of Error Locating Codes

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