An Efficient Reduction Method of a Substrate RC Network Model(Special Section of Selected Papers from the 13th Workshop on Circuits and Systems in Karuizawa)

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概要

• 論文の詳細を見る

• This paper proposes an efficient reduction method for a substrate network model, which is extracted from layout data, to analize a substrate coupling noise. The proposed method adopts in a reduction operation a hierarchic structure of a substrate RC network model, a computational procedure using matrix elements, and an expression of admittance as polynominal in complex frequency s=jw. These techniques improve computational efficiency and are suitable for an implementation. In the example of a triple well CMOS circuit, a reduced model, from 7500 nodes to 5 nodes, has less than 25% errors up to 1GHz.

• 社団法人電子情報通信学会の論文
• 2001-03-01

著者

• Kimura T

  Toshiba Corp. Kawasaki‐shi Jpn

• KIMURA Tomohisa

  Research and Develop Center, Toshiba Corp.

• OKUMURA Makiko

  Department of Electrical & Electronic Engineering, Kanagawa Institute of Technology

• Okumura M

  Department Of Electrical & Electronic Engineering Kanagawa Institute Of Technology

関連論文

• An Efficient Reduction Method of a Substrate RC Network Model(Special Section of Selected Papers from the 13th Workshop on Circuits and Systems in Karuizawa)

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