A Routability Driven Technology Mapping Algorithm for LUT Based FPGA Designs(Special Section on VLSI Design and CAD Algorithms)

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概要

• 論文の詳細を見る

• This paper presents a CAD technology mapping algorithm for LUT-based FPGAs. Since interconnections in an FPGA must be accomplished with limited routing resources, routability is the most important objective in a technology mapping algorithm. To optimize routability, the goal of the algorithm is the production of a design with a minimum interconnection. The Min-cut algorithm[1]-[3]is first used to partition a graph representing a Boolean network into clusters so that the total number of interconnections between clusters is minimum. To decrease further the number of interconnections needed, clusters are then merged into larger clusters by a pairing technique. This algorithm has been tested on the MCNC benchmark circuits. Compared with other LUT-based FPGA mapping algorithms, the algorithm produces better routability characteristics.

• 一般社団法人電子情報通信学会の論文
• 2001-11-01

著者

• Kao Chi-chou

  The Department Of Electrical Engineering National Cheng Kung University

• LAI Yen-Tai

  the Department of Electrical Engineering, National Cheng Kung University

• Lai Yen-tai

  The Department Of Electrical Engineering National Cheng Kung University

関連論文

• A Routability Driven Technology Mapping Algorithm for LUT Based FPGA Designs(Special Section on VLSI Design and CAD Algorithms)

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