Timing Driven Gate Duplication in Technology Independent Phase(Special Section on VLSI Design and CAD Algorithms)

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概要

• 論文の詳細を見る

• We propose a timing driven gate duplication algorithm for the technology independent phase. Our algorithm is a generalization of the gate duplication strategy suggested in [3]. Our technique gets a more global view by duplicating multiple gates at a time. We compare the minimum circuit delay obtained by SIS[4]with the delay obtained by using our gate duplication. Results show that up to 11% improvement in delay can be obtained. Our algorithm does not have an adverse effect on the overall synthesis time, indicating that gate duplication is an efficient strategy for timing optimization.

• 社団法人電子情報通信学会の論文
• 2001-11-01

著者

• Chen Chunhong

  The Department Of Electrical And Computer Engineering University Of Windsor

• SRIVASTAVA Ankur

  the Computer Science Department, University

• SARRAFZADEH Majid

  the Computer Science Department, University

• Srivastava Ankur

  The Computer Science Department University

• Sarrafzadeh Majid

  The Computer Science Department University

関連論文

• Timing Driven Gate Duplication in Technology Independent Phase(Special Section on VLSI Design and CAD Algorithms)

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