A New Clock Routing Algorithm Using Link-Edge Insertion for High Performance IC Design (Special Section of Papers Selected from ITC-CSCC'99)

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As the clock skew is one of the major constraints for high speed synchronous ICs, it must be minimized in order to obtain high performance. But clock skew minimization may increase the total wire length;therefore, clock routing is performed within the given skew bound. Clock routing under the specified skew bound can decrease the total wire length. A new efficient algorithm for bounded clock skew routing using link-edge insertion is proposed in this paper. It satisfies the given skew bound and prevents the total wire length from increasing. Not only the total wire length and delay time minimization algorithm using the new merging point relocatin method but also the clock skew reduction algorithm using link-edge insertion technique for a pair of nodes whose delay difference is large is proposed. The proposed algotithm constructs a new clock routing topology which is a generalized graph model, while most previous methods use only tree-structured routing topology. A new cost function is designed in order to select two nodes for link-edge addition. Using this cost function, delay difference or clock skew is reduced by connecting two nodes whose delay difference is large and distance is small. Furthermore, routing topology construction and wire sizing algorithm is used to reduce the clock delay. The proposed algorithm is implemented in C programming language. The experimental results show that the total wire length can be reduced under the given skew bound.
社団法人電子情報通信学会の論文
2000-06-25

A New Clock Routing Algorithm Using Link-Edge Insertion for High Performance IC Design (Special Section of Papers Selected from ITC-CSCC'99)

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