Design of a Low Power Consumption Pulse-Shaping 1:4 Interpolation FIR Filter for W-CDMA Applications (Special Section on VLSI Design and CAD Algorithms)

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概要

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• This paper presents the design and simulation of a power efficient 1:4 interpolation FIR filter with partitioned look Up Table(LUT) structure. Using the symmetry of the filter coefficients and the contents of the LUT, the area of the proposed filter is minimized. The two filters share the partitioned LUT and activate the LUT selectively to realize the low power operation. Experimental results suggest that the proposed filter reduces the power consumption by 25% and simultaneously reduces the gate area by 7% compared to the previously proposed single-architecture dual-channel filter.

• 社団法人電子情報通信学会の論文
• 2000-12-25

著者

• Chong J‐w

  The Department Of Electronic Engineering Hanyang University

• RYOO Keun-Jang

  the Department of Electronic Engineering, Hanyang University

• CHONG Jong-Wha

  the Department of Electronic Engineering, Hanyang University

• Ryoo Keun-jang

  The Department Of Electronic Engineering Hanyang University

関連論文

• Design of a Low Power Consumption Pulse-Shaping 1:4 Interpolation FIR Filter for W-CDMA Applications (Special Section on VLSI Design and CAD Algorithms)

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