An Iterative Improvement Circuit Partitioning Algorithm under Path Delay Constraints (Special Section on VLSI Design and CAD Algorithms)

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概要

• 論文の詳細を見る

• This paper presents a timing-driven iterative improvement circuit partitioning algorithm under path delay constraints for the general delay model. The proposed algorithm is an extension of the Fiduccia & Mattheyses(FM) method so as to handle path delay constraints and consists of the clustering and iterative improvement phases. In the first phase, we reduce the size of a given circuit, with a new clustering algorithm to obtain a partition in a short computation time. Next, the iterative improvement phase based on the FM method is applied, and then a new path-based timing violation removal algorithm is also performed so as to remove all the timing violations. From experimental results for ISCAS89 benchmarks, we have demonstrated that the proposed algorithm can produce the partitions which mostly satisfy the timing constraints.

• 社団法人電子情報通信学会の論文
• 2000-12-25

著者

• Koide Tetsushi

  Vlsi Design And Education Center The University Of Tokyo

• Minami Jun'ichiro

  The Faculty Of Engineering Hiroshima University:(present Address) Ntt Chugoku Mobile Communications

• Wakabayashi Shin'ichi

  The Faculty Of Engineering Hiroshima University

関連論文

• An Iterative Improvement Circuit Partitioning Algorithm under Path Delay Constraints (Special Section on VLSI Design and CAD Algorithms)

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