A Practical Method for System-Level Bus Architecture Validation (Special Section on VLSI Design and CAD Algorithms)

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概要

• 論文の詳細を見る

• This paper presents a system-level bus architecture validation technique and shows its application to a consumer product design. This technique enables the entire system to be validated with bus cycle accuracy using bus architecture level models derived from their corresponding behavioral level models. Experimental results from a digital still camera(DSC) system design show that our approach offers much faster simulation speed than register transfer level(RTL) simulators. Using this fast and accurate validation technique, bus architecture designs, validations and optimizations can be effectively carried out at system-level and total turn around time of system designs can be reduced dramatically.

• 社団法人電子情報通信学会の論文
• 2000-12-25

著者

• Motohara A

  Advanced Lsi Technology Development Center Corporate Semiconductor Development Division Matsushita E

• Mizuno Masanobu

  Advanced Lsi Technology Development Center Corporate Semiconductor Development Division Matsushita E

• TAKEMURA Kazuyoshi

  Advanced LSI Technology Development Center, Corporate Semiconductor Development Division, Matsushita

• MOTOHARA Akira

  Advanced LSI Technology Development Center, Corporate Semiconductor Development Division, Matsushita

• Takemura K

  Advanced Lsi Technology Development Center Corporate Semiconductor Development Division Matsushita E

関連論文

• A Practical Method for System-Level Bus Architecture Validation (Special Section on VLSI Design and CAD Algorithms)

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