Dynamic Fast Issue(DFI) Mechanism for Dynamic Scheduled Processors (Special Section on VLSI Design and CAD Algorithms)

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概要

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• Superscalar processors can achieve increased performance by issuing instructions Out-of-Order(OoO) from the original instruction stream. Implementing an OoO instruction scheme requires a hardware mechanism to prevent incorrectly executed instructions from updating registers values. In addition, performance decreases if data dependencies, a branch or a trap among instructions appears. To this end we propose a new mechanism named Dynamic Fast Issue(DFI) mechanism to issue instructions in an OoO fashion to multiple parallel functional units without considerable hardware complexity. The above system, which will be implemented in our Superscalar Functional Assignments Register Microprocessor(FARM) [1], solves data dependencies, supports precise interrupt and branch prediction, which are the main problems associated with the dynamic scheduling of instructions in superscalar machines. Results are written only once, Write-once, directly into the register file(RF). To ensure that results are written in order in their appropriate output registers, a record of instruction order and state is maintained by a status buffer(STB). A 64 entries integrated register file is implemented to hold both renamed and logical registers. To recover the processor state from an interrupt or a branch missprediction, a status buffer(STB) and a recovery list table(RLT) are implemented. Novel aspects of the above system architecture as well as the principle underlying this process and the constraints that must be met is presented. Performance evaluation results are performed through full-pipelined-level architectural simulator and SPECint95 benchmark programs.

• 社団法人電子情報通信学会の論文
• 2000-12-25

著者

• Abdallah Ben

  The University Of Electro-communications

• Sowa Masahiro

  The University Of Electro-communications

• SAREM Mudar

  the National Computing Laboratories at Hua Zhong University of Science and Technology

関連論文

• A Performance Measure for the Scheduling of Typed Task Systems with Communication Costs
• Dynamic Fast Issue(DFI) Mechanism for Dynamic Scheduled Processors (Special Section on VLSI Design and CAD Algorithms)
• An FPGA-Based Information Detection Hardware System Employing Multi-Match Content Addressable Memory

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