High-Speed Low-Power CMOS Pipelined Analog-to-Digital Converter (Special Section of Papers Selected from ITC-CSCC '98)

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概要

• 論文の詳細を見る

• This paper describes a 10-bit 40-MS/s pipelined A/D converter implemented in a 0.8-μm double-poly, double-metal CMOS process. This A/D converter achieves low power dissipation of 36-mW at 5-V power supply. A 1.5-bit/stage pipelined architecture allows large correction range for comparator offset, and performs fast interstage signal processing. For high speed and low power operation, the sample-and-hold amplifier is designed using op-amp sharing technique and dynamic comparator In addition, fully-differential folded-cascode op amp with gain-boosting stage is designed by an automatic design tool. When 10-MHz input signal is applied, SNDR is 55.0 dB, and SNR is 56.7 dB. The DNL and INL exhibit ±0.6 LSB, +1/ -0.75 LSB respectively.

• 社団法人電子情報通信学会の論文
• 1999-06-25

著者

• Yu Sang-dae

  Faculty Of The School Of Electronic And Electrical Engineering Kyungpook National University

• Lee Dong-ho

  Faculty Of The School Of Electronic And Electrical Engineering Kyungpook National University

• JU Ri-A

  Candidate of Ph.D. of the Department of Electronics, Graduate School, Kyungpook Na-tional University

• Ju Ri-a

  Candidate Of Ph.d. Of The Department Of Electronics Graduate School Kyungpook Na-tional University

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