Parallel Test Structure in Latch Based Asynchronous Pipeline (Special Section on VLSI Design and CAD Algorithms)

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概要

• 論文の詳細を見る

• Detecting the stuck-at-pass faults in the eventdriven latches is the main difficult in testing latch based asynchronous pipeline. In this paper we proposed a parallel test structure to ease this problem.

• 社団法人電子情報通信学会の論文
• 1999-11-25

著者

• Choy C‐s

  Faculty Of Electronic Engineering The Chinese University Of Hong Kong

• Chan C‐f

  Faculty Of Electronic Engineering The Chinese University Of Hong Kong

• YANG Jing-ling

  Faculty of Electronic Engineering, The Chinese University of Hong Kong

• CHOY Chiu-sing

  Faculty of Electronic Engineering, The Chinese University of Hong Kong

• CHAN Cheong-Fat

  Faculty of Electronic Engineering, The Chinese University of Hong Kong

• Yang Jing-ling

  Faculty Of Electronic Engineering The Chinese University Of Hong Kong

関連論文

• Parallel Test Structure in Latch Based Asynchronous Pipeline (Special Section on VLSI Design and CAD Algorithms)

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