A VLSI Scan-Chain Optimization Algorithm for Multiple Scan-Paths (Special Section on VLSI Design and CAD Algorithms)

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概要

• 論文の詳細を見る

• This paper presents an algorithm for the scanchain optimization problem in multiple-scan design methodology. The proposed algorithm, which consists of four phases, first determines pairs of scan-in and scan-out pins (Phase 1), and then assigns flip-flops to scan-paths by using a graph theoretical method (Phase 2). Next the algorithm decides connection-order of flip-flops in each scan-path by using TSP (Traveling Salesman Problem) heuristics (Phase 3), and finally exchanges flip-flops among scan-paths in order to reduce total scan-path length (Phase 4). Experiments using actual design data show that, for ten scan-paths, our algorithm achieved a 90% reduction in scan-test time at the expense of a 7% total scan-path length increase as compared with the length of a single optimized scan-path. Also, our algorithm produced less total scan-path length than other three possible algorithms in a reasonable computing time.

• 社団法人電子情報通信学会の論文
• 1999-11-25

著者

• Kubo M

  Tokoha Gakuen Univ. Shizuoka‐shi Jpn

• Edahiro M

  C&c Media Research Laboratories Nec Corporation

• KOBAYASHI Susumu

  C&C Media Research Laboratories, NEC Corporation

• EDAHIRO Masato

  C&C Media Research Laboratories, NEC Corporation

• KUBO Mikiko

  Logistics and Information Engineering, Tokyo University of Mercantile Marine

関連論文

• A VLSI Scan-Chain Optimization Algorithm for Multiple Scan-Paths (Special Section on VLSI Design and CAD Algorithms)

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