A Partially Explicit Method for Efficient Symbolic Checking of Language Containment (Special Section on VLSI Design and CAD Algorithms)
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概要
- 論文の詳細を見る
There are two approaches for formal verification of sequential designs or finite state machines: language containment checking and symbolic model checking. To verify designs of practical size, in these two approaches, designs are represented symbolically, in practice, by ordered binary decision diagrams. In the conventional algorithm for language containment checking, finite automata given as specifications are also represented symbolically. This paper proposes a new method, called partially explicit method for checking language containment. By representing states of finite automata given as specifications explicitly, this method can remove redundant computations, and as a result, provide better performance than the conventional method which uses the product machines of designs and specifications. The experimental results show that this approach is effective in checking language containment symbolically.
- 社団法人電子情報通信学会の論文
- 1999-11-25
著者
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Hamaguchi Kiyoharu
Department Of Bioinformatic Engineering Guraduate School Of Information Science And Technology Osaka
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Hamaguchi Kiyoharu
Department Of Informatics And Mathematical Science Graduate School Of Engineering Science Osaka Univ
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Kashiwabara Toshinobu
Department Of Bioinformatic Engineering Guraduate School Of Information Science And Technology Osaka
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Kashiwabara Toshinobu
Department Of Informatics And Mathematical Science Graduate School Of Engineering Science Osaka Univ
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ICHIHARA Michiyo
Omron Software Corporation
関連論文
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- A Partially Explicit Method for Efficient Symbolic Checking of Language Containment (Special Section on VLSI Design and CAD Algorithms)
- Regular Temporal Logic Expressively Equivalent to Finite Automata and Its Application to Logic Design Verification
- Algorithms for Generating Maximum Weight Independent Sets in Circle Graphs, Circular-Arc Overlap Graphs, and Spider Graphs
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