Logic Minimization for Large-Scale Networks Based on Multi-Signal Implications (Special Section on VLSI Design and CAD Algorithms)

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概要

• 論文の詳細を見る

• This paper presents a novel implication-based method for logic minimization in large-scale, multi-level networks. It significantly reduces network size through repeated addition and removal of redundant subnetworks, utilizing multi-signal implications and relationships among these implications. These are handled on a transitive implication graph, proposed in this paper, which offers the practical use of implications for logic minimization. The proposed method holds great promise for the achievement of an interactive logic design environment for large-scale networks.

• 社団法人電子情報通信学会の論文
• 1999-11-25

著者

• Yoshimura T

  C&c Media Research Labs Nec Corporation

• YUGUCHI Masayuki

  C&C Media Research Labs, NEC Corporation

• WAKABAYASHI Kazutoshi

  C&C Media Research Labs, NEC Corporation

• YOSHIMURA Takeshi

  C&C Media Research Labs, NEC Corporation

• Yuguchi Masayuki

  C&c Media Research Labs Nec Corporation

• Wakabayashi K

  Nec Multimedia Res. Lab. Kawasaki‐shi Japan

関連論文

• Logic Minimization for Large-Scale Networks Based on Multi-Signal Implications (Special Section on VLSI Design and CAD Algorithms)

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