A VLSI Algorithm for Modular Division Based on the Binary GCD Algorithm(Special Section on Discrete Mathematics and Its Applications)

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概要

• 論文の詳細を見る

• An algorithm for modular division which is suitable for VLSI implementation is proposed. It is based on the plus-minus algorithm which is a modification of the binary method for calculating the greatest common divisor(GCD). The plus-minus algorithm for calculating GCD is extended for performing modular division. A modular division is carried out through iteration of simple operations, such as shifts and addition/subtractions. A redundant binary representation is employed so that addition/subtractions are performed without carry propagation. A modular divider based on the algorithm has a linear array structure with a bit-slice feature and carries out an n-bit modular division in O(n) clock cycles, where the length of clock cycle is constant independent of n.

• 社団法人電子情報通信学会の論文
• 1998-05-25

著者

• Takagi N

  Nagoya Univ. Nagoya‐shi Jpn

• TAKAGI Naofumi

  the Department of Information Engineering, Nagoya University

関連論文

• A VLSI Algorithm for Modular Division Based on the Binary GCD Algorithm(Special Section on Discrete Mathematics and Its Applications)

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