Application of Full Scan Design to Embedded Memory Arrays (Special Section of Selected Papers from the 9th Karuizawa Workshop on Circuits and Systems)

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概要

• 論文の詳細を見る

• This paper describes the design and evaluation of fully scannable embedded memory arrays. A memory array, such as a register file, is made scannable by adding a small auxiliary circuit including a counter and multiplexers. Plural memory arrays can be chained into a single scan path along with ordinary flip-flops. Detailed configuration and implementation of the scannable CMOS and bipolar LCML register file macros are discussed. The overhead ratio of the CMOS register file macro with 16-word by 16-bit results in an 8.6% transistor count and a 6.4% die area. The access time overhead is 7.8% and the set-up time increases by about 50 ps. Bipolar LCML register file macros have been applied to gate array LSIs which have successfully achieved average stuck-at fault coverage of 99.2%.

• 社団法人電子情報通信学会の論文
• 1997-03-25

著者

• Ishiura Nagisa

  Department Of Information Systems Engineering Osaka University

• Ishiura Nagisa

  Department Of Informatics

• YANO Seiken

  1st Computers Operations Unit, NEC Corp.

• AKAGI Katsutoshi

  NEC Electronics, Inc.,

• INOHARA Hiroki

  NEC Systems Laboratory, Inc.,

• Yano Seiken

  1st Computers Operations Unit Nec Corp.

• Akagi Katsutoshi

  Nec Electronics Inc.

• Inohara Hiroki

  Nec Systems Laboratory Inc.

関連論文

• FOREWORD
• Embedded Memory Array Testing Using a Scannable Configuration (Special Section on VLSI Design and CAD Algorithms)
• Application of Full Scan Design to Embedded Memory Arrays (Special Section of Selected Papers from the 9th Karuizawa Workshop on Circuits and Systems)

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