A Study of the Signal-to-Noise Ratio of a High-Speed Current-Mode CMOS Sample-and-Hold Circuit (Special Section on VLSI Design and CAD Algorithms)

概要

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Our study investigated the realization of a high-precision MOS current-mode circuit. Simple studies have implied that it is difficult to achieve a high signal-to-noise ratio (S/N) in a current-mode circuit. Since the signal voltage at the internal node is suppressed, the circuit is sensitive to various noise sources. To investigate this, we designed and fabricated a current-mode sample-and-hold circuit with a 3 V power supply and a 20 MHz clock speed, using a standard CMOS 0.6μm device process. The measured S/N reached 57 dB and 59 dB in sample mode, and 51 dB and 54 dB in sample-and-hold mode, with ±115 μA from a 3 V power supply and ±220 μA from a 5 V power supply of in-put currents and a 10MHz noise bandwidth. The S/N analysis based on an actual circuit was done taking device noise sources and the fold-over phenomena of noise in a sampled system into account. The calculation showed 66.9 dB of S/N in sample mode and 59.5 dB in sample-and-hold-mode with ±115 μA of input current. Both the analysis and measurement indicated that 60dB of S/N in sample mode with a 10 MHz noise bandwidth is an achievable value for this sample-and-hold circuit. It was clear that the current-mode approach limits the S/N performance because of the voltage suppression method. This point should be further studied and discussed.
社団法人電子情報通信学会の論文
1997-10-25