Efficient Routability Checking for Global Wires in Planar Layouts
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概要
- 論文の詳細を見る
In VLSI and printed wiring board design, routing process usually consists of two stages: the global routing and the detailed routing. The routability checking is to decide whether the global wires can be transformed into the detailed ones or not. In this paper, we propose two graphs, the capacity checking graph and the initial flow graph, for efficient routability checking in planar layouts.
- 社団法人電子情報通信学会の論文
- 1997-10-25
著者
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Kawaguchi Yasushi
Department Of Rheumatology Tokyo Women's Medical University
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Kawaguchi Yasushi
The Faculty Of Engineering Nagoya University:(present Address)fujitsu Limited
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Hirata Tomio
The Faculty Of Engineering Nagoya University
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ISO Naoyuki
the Faculty of Engineering, Nagoya University
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Iso N
Nagoya Univ Nagoya‐shi Jpn
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