Logic Synthesis for Cellular Architecture FPGAs Using EXOR Ternary Decision Diagrams (Special Section on VLSI Design and CAD Algorithms)

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概要

• 論文の詳細を見る

• In this paper, an efficient approach to the synthesis of CA (Cellular Architecture)-type FPGAs is presented. To exploit the array structure of cells in CA-type FPGAs, logic expressions called Maitra terms which can be mapped directly to the cell arrays are generated by using ETDDs (EXOR Ternary Decision Diagrams). Since a traversal of the ETDD is sufficient to generate a Maitra term which takes O(n) steps where n is the number of nodes in the ETDD, Maitra terms are generated very efficiently. The experiments show that the proposed method generates better results than existing methods.

• 社団法人電子情報通信学会の論文
• 1997-10-25

著者

• Park S

  Sungkyunkwan Univ. Suwon Kor

• Park S

  Sungkyunkwan Univ. Kyunggi‐do Kor

• LEE Gueesang

  the Department of Computer Science, Chonnam University

• PARK Sungju

  the Department of Computer Engineering, Hanyang University

• Lee Gueesang

  The Department Of Computer Science Chonnam University

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• Logic Synthesis for Cellular Architecture FPGAs Using EXOR Ternary Decision Diagrams (Special Section on VLSI Design and CAD Algorithms)

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