A Novel PE-based Architecture for Lossless LZ Compression

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概要

• 論文の詳細を見る

• This paper proposes a novel VLSI architecture capable of processing the Lempel-Ziv-based data compression algorithm very fast. The architecture is composed of five main blocks, i.e., a PE-based Match Block, a Consecutive Hit Checker, a Pointer Generator, a Length Generator, and a Code Packer. Flexibility of the PE-based structure makes it possible to adapt to various buffer sizes without any loss of speed or additional control overhead. Since it is designed as a VLSI-oriented architecture, it has simple control logic circuitry. It processes exactly one character per clock cycle and the update of a dictionary buffer is automatically done, therefore it does not require additional accumulated shift operations to prepare for the dictionary buffer. The shift operations have been major problems commonly found in most other architectures [1]-[4]. When implemented with the currently available 0.5 μm CMOS technology, it is proven by critical path analysis that the architecture can achieve over 100 mega samples (characters) per second with a clock frequency of 100 MHz. This is fast enough for real time data compression for many applications.

• 社団法人電子情報通信学会の論文
• 1997-01-25

著者

• Lee T

  Hyundai Electronics Seoul Kor

• Lee Y

  Hongik Univ. Seoul Kor

• LEE Yong

  VLSI & CAD Laboratory, Department of Electronic Engineering, Yonsei University

• LEE Tae

  VLSI & CAD Laboratory, Department of Electronic Engineering, Yonsei University

• PARK Kyu

  VLSI & CAD Laboratory, Department of Electronic Engineering, Yonsei University

• Park Kyu

  Vlsi & Cad Laboratory Department Of Electronic Engineering Yonsei University

関連論文

• A Fast Finite Field Multiplier Architecture for High-Security Elliptic Curve Cryptosystems
• A Novel PE-based Architecture for Lossless LZ Compression
• A 32-bit RISC Microprocessor with DSP Functionality : Rapid Prototyping

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