Design of 12-Bit 500MHz CMOS Current-Mode DAC With Deglitch Circuit--Design of Wide Bandwidth Digital to Analog Converter (Devices:先端デバイスの基礎と応用に関するアジアワークショップ)

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概要

• 論文の詳細を見る

• This paper describes a 12-bit 500MHz CMOS current-mode Digital to Analog Converter (DAC) consisting of 6 MSB current cell matrix stage, 2 MSB unary current source stage, and 4 LSB binary weighting stage. The linearity errors (DNL/INL) resulting from random and system errors are reduced by the proposed triple diagonally symmetrical centroid sequencing methodology. A new deglitch circuit is proposed to control a crossing point of signal and minimize a glitch energy. The simulation results show a conversion rate of 500MHz, DNL/INL of ±0.65LSB/±0.8LSB, a glitch energy of 7.5pV・sec and a power dissipation of 84mW at 3.3V.

• 社団法人電子情報通信学会の論文
• 2003-06-24

著者

• Yoon Kwang

  Dept. Of Electronic Engineering Inha University

• Cho Hyun

  Dept. Of Electronic Engineering Inha University

関連論文

• Design of 12-Bit 500MHz CMOS Current-Mode DAC With Deglitch Circuit--Design of Wide Bandwidth Digital to Analog Converter (Devices:先端デバイスの基礎と応用に関するアジアワークショップ)
• Design of 12-Bit 500MHz CMOS Current-Mode DAC With Deglitch Circuit--Design of Wide Bandwidth Digital to Analog Converter (Devices:先端デバイスの基礎と応用に関するアジアワークショップ)

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