Deadlock avoidance in construction of n FSM's

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概要

• 論文の詳細を見る

• Communication systems and their protocols can be modeled in n Finite State Machines (FSM's)which exchange messages over m FIFO, error-free and unidirectional channels. In construction of these FSM's, a designer may easily fall in creating some logical errors, such as deadlocks which imply that at least two FSM's are waiting each other to receive messages, but no message is sent to them. This paper proposes some design rules to protect a designer from creating deadlocks.eng

• 一般社団法人情報処理学会の論文
• 1989-10-16

著者

• 張 尭学

  東大

• 白鳥 則郎

  東大

• 野口 正一

  東大

関連論文

• Deadlock avoidance in construction of n FSM's

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