A Genetic Algorithm for the Rectilinear Steiner Tree Problem in VLSI Interconnect Layout (特集:システムLSIの設計技術と設計自動化)

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概要

• 論文の詳細を見る

• This paper proposes a genetic algorithm for generating a set of rectilinear Steiner trees for the interconnect optimization problem in VLSI layout design. The algorithm produces a set of rectilinear Steiner trees, whose geometrical and timing characteristics are different each other. In the proposed genetic algorithm, each chromosome represents the topological structure of a Steiner tree. An evaluation function is given to map it into the layout of a Steiner tree. Steiner trees produced by the algorithm are Pareto-optimal with respect to the total wire length and the maximum propagation delay, and the user can choose any tree among those solutions as a final routing solution. Experimental results show that the algorithm efficiently produces a set of alternative routes in VLSI interconnect optimization.

• 一般社団法人情報処理学会の論文
• 2002-05-15

著者

• Wakabayashi Shin'ichi

  Hiroshima University

関連論文

• A Genetic Algorithm for the Rectilinear Steiner Tree Problem in VLSI Interconnect Layout (特集:システムLSIの設計技術と設計自動化)

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