非同期イベント方式パラレル故障シミュレータ

概要

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Digital fault simulation is used for verifying the validity of test sequences intended to detect and locate faults in logic circuits. Parallel fault simulator described here simulates a fault-free circuit concurrently with the propagation effect of a set of Stuck-at type faults on the circuit. It employs selective tracing of active network path and is therefore applicable to both asynchronous and synchronous circuits. These circuits can be simulated at the hybrid level (a combination of gates. flip-flops and functional elements). The simulator uses three simulation values: ZERO,ONE and UNKNOWN. The third UNKNOWN value is just for efficient initialization of the circuit. That is , as long as the fault-free circuit contains the UNKNOWN value ,the simulator simulates the Boolean logic function using the three values. After the fault-free circuit was stabilized to a certain known condition, it uses only two values to simulate: ZERO and ONE.
一般社団法人情報処理学会の論文
1976-07-15