ディジタル機器の論理設計検査プログラムGPLS-Iについて

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概要

• 論文の詳細を見る

• An application program named GPLS-I (for General Purpose Logic Simulator Version I) has been developed to check the validity of logical design while it is still on the drawing board. GPLS-I can execute logic simulation of (1) synchronous logic circuit, (2) asynchronous logic circuits, and (3) mixtures of both types of circuits when basic logical design is over (AND,OR level), or when the logic circuit is expressed in terms of actual logic elements such as Texas Instruments' J-K flip-flops in dual-in-line packages, or if the designer finds it useful, when the circuit is a mixture of various stages of logical design as is often found in the designer's memos. The inout data for GPLS-I are the connections of logic elements and input signals applied to the logic circiut. From these data GPLS-I prints out the static time chart of logical 0 or logical 1 at the arbitrarily specified terminals of arbitrarily specified logic elements. The times at which logical signals are to be printed out can also be predetemined. Signal voltage levels are treated as either high (logical 1) or low (logical 0). GPLS-I is best suited for the design check of medium to small scale industrial digital systems. Several cases og actual design check have proved that GPLS-I is a very useful and convenient tool. In this paper the outline of GPLS-I is explaned and an example of design check by means of GPLS-I is given. Also the algorithm and program system structure are described in relative detail.

• 一般社団法人情報処理学会の論文
• 1969-01-15

著者

• 河村 佳洋

  日本アイビーエム株式会社

• 荒牧 達

  住友電気工業株式会社

• 荒牧 達

  住友電気工業システム事業部

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