Fast LISP Machine and List-Evaluation Processor EVAL II : Processor Architecture and Hardware Configuration

概要

論文の詳細を見る
This paper describes the architecture and the hardware configuration of an experimental LISP machine developed with the primary emphasis on high-speed list processing. This machine consists of a processor EVAL II, an I/O processor and a common main memory; the EVAL II processes data of list structure, the I/O processor executes LISP input/output functions and manages external memories, such as files, and the main memory chiefly stores list cells. The EVAL II is a newly designed processor suitable for list processing. To develop such a processor, no existing microprocessor is used. The EVAL II has common address/data buses because it processes mainly address pointers. The unique hardware features of the EVAL II include CARCDR-operation facility which executes list searching at high speed in parallel to ALU operations and/or branch operations, and the dispatch facility by which the program efficiently branches to a destination according to a list-cell type or a function type. Parallel processing (branch operation and other operations) and pipeline processing are also executed efficiently. The machine executes benchmark programs as fast as LISP systems on very large general-purpose computers. The dynamic measurements show that this architecture is suitable for LISP machines.
一般社団法人情報処理学会の論文
1985-10-21