A Gate Placement Algorithm for One-Dimensional Arrays

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概要

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• This paper deals with the design procedure of MOS one-dimensional arrays. A one-dimensional array consists of single-type elementary circuits such as NAND or NOR gates. Gates in an array may be arranged in an arbitary order. The pupose of this paper is to find an optimal gate ordering in such a sense that the corresponding chip area is to be smallest. An algorithm presented in this paper searches for an optimal wire ordering rather than an optimal gate ordering. The corresponding gate ordering can be achieved according to the wire ordering obtained. The algorithm is sub-optimal in a sense that it reaches an optimal solution if sufficient storage and execution time are permitted. It has been programmed on the FACOM 230-45/S computer and has proved successful experiments.

• 一般社団法人情報処理学会の論文
• 1978-04-20

著者

• Asano Tetsuo

  Faculty Of Engineering Osaka Electro-communication University

• Tanaka Kokichi

  Faculty Of Engineering Science Osaka University

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