Parallel Fault Simulation Techniques for Large Digital Circuits Including Functional Elements

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概要

• 論文の詳細を見る

• Parallel fault simulation techniques for functional elements are described in this paper. This technique can be applied to synchronous and asynchronous large digital circuits consisting of gates, flip-flops, ROMs, RAMs, Content Addressable Memories and Register Files.

• 一般社団法人情報処理学会の論文

著者

• Yamada Akihiko

  System Development Department Computer Engineering Division Nippon Electric C0. Ltd.

• WAKATSUKI Nobuo

  System Development Department, Computer Engineering Division Nippon Electric C0., Ltd.

• TOMITA Kyouji

  System Development Department, Computer Engineering Division Nippon Electric C0., Ltd.

• Tomita Kyouji

  System Development Department Computer Engineering Division Nippon Electric C0. Ltd.

• Wakatsuki Nobuo

  System Development Department Computer Engineering Division Nippon Electric C0. Ltd.

関連論文

• Parallel Fault Simulation Techniques for Large Digital Circuits Including Functional Elements

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