Electrical Characteristics of Au Doped Si CMOS FET's without Isolation Layer

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概要

• 論文の詳細を見る

• A new geometrical design of CMOS device arranged on the gold doped intrinsic-type silicon substrate was presented. P-channel MOS (pMOS) and n-channel MOS (nMOS) FET's were fabricated in series on the substrate without isolation layer, so called well-region. The spacing between pMOS and nMOS FET's was changed from 60μm to 0μm. In order to examine the basic feature, drain current-drain voltage characteristics of each MOS FET were measured. The characteristics were similar to those observed in conventional MOS FET's. Digital inverters were prepared to demonstrate the electrical performance of CMOS FET's. Input-output characteristic of the inverter which has zero spacing (directly contacted) between pMOS and nMOS FET's, showed a curve to endure the practical use as well as the inverter having non-zero spacing between both FET's.

• 東海大学の論文

著者

• Titiroongruang W

  Department Of Electronics Faculty Of Engineering King Mongkut's Institute Of Technology Ladkrab

• Titiroongruang Wisut

  Department Of Electronics Faculty Of Engineering King Mongkut's Institute Of Technology

• Supadech S

  Department Of Electronics Faculty Of Engineering King Mongkut's Institute Of Technology Ladkrab

• Supadech Somkiat

  Department Of Electronics Faculty Of Engineering King Mongkut's Institute Of Technology

• Parnklang Jirawath

  Department of Electronics, Faculty of Engineering, King Mongkut's Institute of Technology Ladkrabang

• Parnklang Jirawath

  Department Of Electronics Faculty Of Engineering King Mongkut's Institute Of Technology Ladkrab

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• Electrical Characteristics of Au Doped Si CMOS FET's without Isolation Layer

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