Design and Implementation of a Handshake Join Architecture on FPGA

スポンサーリンク

概要

• 論文の詳細を見る

• A novel design is proposed to implement highly parallel stream join operators on a field-programmable gate array (FPGA), by examining handshake join algorithm for hardware implementation. The proposed design is evaluated in terms of the hardware resource usage, the maximum clock frequency, and the performance. Experimental results indicate that the proposed implementation can handle considerably high input rates, especially at low match rates. Results of simulation conducted to optimize size of buffers included in join and merge units give a new intuition regarding static and adaptive buffer tuning in handshake join.

• The Institute of Electronics, Information and Communication Engineersの論文
• 2012-12-01

著者

• YOSHINAGA Tsutomu

  the Graduate School of Information Systems, The University of Electro-Communications

• KAWASHIMA Hideyuki

  the University of Tsukuba

• OGE Yasin

  the Graduate School of Information Systems, The University of Electro-Communications

• MIYOSHI Takefumi

  the Graduate School of Information Systems, The University of Electro-Communications

関連論文

• D-6-9 Compiler Assisted Scheduling Scheme with Low-cost Runtime Support for Control Predicated ILP
• Design and Implementation of a Handshake Join Architecture on FPGA

スポンサーリンク