A Multi-Gigabit Parallel Demodulator and Its FPGA Implementation

スポンサーリンク

概要

• 論文の詳細を見る

• This letter presents the architecture of multi-gigabit parallel demodulator suitable for demodulating high order QAM modulated signal and easy to implement on FPGA platform. The parallel architecture is based on frequency domain implementation of matched filter and timing phase correction. Parallel FIFO based delete-keep algorithm is proposed for timing synchronization, while a kind of reduced constellation phase-frequency detector based parallel decision feedback PLL is designed for carrier synchronization. A fully pipelined parallel adaptive blind equalization algorithm is also proposed. Their parallel implementation structures suitable for FPGA platform are investigated. Besides, in the demonstration of 2Gbps demodulator for 16QAM modulation, the architecture is implemented and validated on a Xilinx V6 FPGA platform with performance loss less than 2dB.

• The Institute of Electronics, Information and Communication Engineersの論文
• 2012-08-01

著者

• LIN Changxing

  the Institute of Electronic Engineering, China Academy of Engineering Physics

• SHAO Beibei

  the Department of Engineering Physics, Tsinghua University

• ZHANG Jian

  the Institute of Electronic Engineering, China Academy of Engineering Physics

関連論文

• A Multi-Gigabit Parallel Demodulator and Its FPGA Implementation

スポンサーリンク