An Improved Hybrid LUT-Based Architecture for Low-Error and Efficient Fixed-Width Squarer

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概要

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• In this paper, an improved hybrid LUT-based architecture for low-error and efficient fixed-width squarer circuits is presented in which LUT-based and conventional logic circuits are employed together to achieve the good trade-off between hardware complexity and performance. By exploiting the mathematical identities and hybrid architecture, the mean error and mean squarer error of the proposed squarer are reduced by up to 40%, compared with the best previous method presented in literature. Moreover, the proposed method can improve the speed and reduce the area of the squarer circuit. The implementation and chip measurement results in 0.18-µm CMOS technology are also presented and discussed.

• 2012-07-01

著者

• PHAM Cong-Kha

  the Department of Electronic Engineering, The University of Electro-Communications

• HOANG Van-Phuc

  the Department of Electronic Engineering, The University of Electro-Communications

関連論文

• Efficient LUT-Based Truncated Multiplier and Its Application in RGB to YCbCr Color Space Conversion
• An Improved Hybrid LUT-Based Architecture for Low-Error and Efficient Fixed-Width Squarer
• Low Complexity Logarithmic and Anti-Logarithmic Converters for Hybrid Number System Processors and DSP Applications

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