A Self-Timed SRAM Design for Average-Case Performance

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概要

• 論文の詳細を見る

• This paper presents a self-timed SRAM system employing new memory segment technique that divides memory cell arrays into multiple regions based on its latency, not the size of the memory cell array. This is the main difference between the proposed memory segmentation technique and the conventional method. Consequently, the proposed method provides a more efficient way to reduce the memory access time. We also proposed an architecture of dummy cell and completion signal generator for the handshaking protocol. We synthesized a 8MB SRAM system consisting of 16 512K memory blocks using Hynix 0.35-µm CMOS process. Our implantation shows 15% higher performance compared to the other systems. Our implementation results shows a trade-off between the area overhead and the performance for the number of memory segmentation.

• 2011-08-01

著者

• Song Young-jun

  The Chungbuk Bit Research-oriented University Consortium Chungbuk National University

• KIM Sang-Choon

  Division of Electronics and Information Communication Engineering, Kangwon National University

• LEE Je-Hoom

  Division of Electronics and Information Communication Engineering, Kangwon National University

• Lee Je-hoom

  Division Of Electronics And Information Communication Engineering Kangwon National University

• Kim Sang-choon

  Division Of Electronics And Information Communication Engineering Kangwon National University

関連論文

• A Self-Timed SRAM Design for Average-Case Performance
• High-Speed FPGA Implementation of the SHA-1 Hash Function

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