High-Speed and Low-Complexity Decoding Architecture for Double Binary Turbo Code

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概要

• 論文の詳細を見る

• We propose a high-speed and low-complexity architecture for the very large-scale integration (VLSI) implementation of the maximum a posteriori probability (MAP) algorithm suited to the double binary turbo decoder. For this purpose, equation manipulations on the conventional Linear-Log-MAP algorithm and architectural optimization are proposed. It is shown by synthesized simulations that the proposed architecture improves speed, area and power compared with the state-of-the-art Linear-Log-MAP architecture. It is also observed that the proposed architecture shows good overall performance in terms of error correction capability as well as decoder hardwares speed, complexity and throughput.

• （社）電子情報通信学会の論文
• 2011-11-01

著者

• BAEK Kwang-Hyun

  School of Electrical and Electronics Engineering, Chung-Ang University

• Lee Jeong

  School Of Electrical And Electronics Engineering Chung-ang University

• Lee Jeong

  School Of Electrical And Electronics Eng. Chung-ang University

• Baek Kwang-hyun

  School Of Electrical And Electronics Engineering Chung-ang University

• Kwon Kon-woo

  School Of Electrical And Computer Engineering Purdue University

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