Multi-Stage Decoding Scheme with Post-Processing for LDPC Codes to Lower the Error Floors

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概要

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• In this letter, we propose a multi-stage decoding scheme with post-processing for low-density parity-check (LDPC) codes, which remedies the rapid performance degradation in the high signal-to-noise ratio (SNR) range known as error floor. In the proposed scheme, the unsuccessfully decoded words of the previous decoding stage are re-decoded by manipulating the received log-likelihood ratios (LLRs) of the properly selected variable nodes. Two effective criteria for selecting the probably erroneous variable nodes are also presented. Numerical results show that the proposed scheme can correct most of the unsuccessfully decoded words of the first stage having oscillatory behavior, which are regarded as a main cause of the error floor.

• 2011-08-01

著者

• Chung Habong

  School Of Electronics And Electrical Engineering Hongik University

• Park Hosung

  Department Of Computer Engineering Chungnam National University

• No Jong-seon

  Department Of Eecs Inmc Seoul National University

• Shin Beomkyu

  Department Of Electrical Engineering And Computer Science Inmc Seoul National University

• PARK Hosung

  Department of Electrical Engineering and Computer Science, INMC, Seoul National University

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