An Energy Efficient Sensor Network Processor with Latency-Aware Adaptive Compression

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概要

• 論文の詳細を見る

• This paper proposed a novel platform for sensor nodes to resolve the energy and latency challenges. It consists of a processor, an adaptive compressing module and several compression accelerators. We completed the proposed chip in a 0.18µm HJTC CMOS technology. Compared to the software-based solution, the hardware-assisted compression reduces over 98% energy and 212% latency. Besides, we balanced the energy and latency metric using an adaptive module. According to the scheduling algorithm, the module tunes the state of the compression accelerator, as well as the sampling frequency of the online sensor. For example, given a 9µs constraint for a 1-byte operation, it reduces 34% latency while the energy overheads are less than 5%.

• 2011-07-01

著者

• Wang Jue

  Electronic Engineering Department Tsinghua University

• Yang Huazhong

  Electronic Engineering Dep. Tsinghua Univ.

• Yang Huazhong

  Electronic Engineering Department Tsinghua University

• Liu Yongpan

  Electronic Engineering Dep. Tsinghua Univ.

• Liu Yongpan

  Electronic Engineering Department Tsinghua University

• LI Shuangchen

  Electronic Engineering Department, Tsinghua University

• YING Beihua

  Electronic Engineering Department, Tsinghua University

• Ying Beihua

  Electronic Engineering Department Tsinghua University

• Li Shuangchen

  Electronic Engineering Department Tsinghua University

関連論文

• An Energy Efficient Sensor Network Processor with Latency-Aware Adaptive Compression
• Lifetime-Aware Battery Allocation for Wireless Sensor Network under Cost Constraints

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