A Duobinary Signaling for Asymmetric Multi-Chip Communication

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概要

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• Duobinary signaling has been introduced into asymmetric multi-chip communications such as DRAM or display interfaces, which allows a controlled amount of ISI to reduce signaling bandwidth by 2/3. A x2 oversampled equalization has been developed to realize Duobinary signaling. Symbol-rate clock recovery form Duobinary signal has been developed to reduce power consumption for receivers. A Duobinary transmitter test chip was fabricated with 90-nm CMOS process. A 3.5dB increase in eye height and a 1.5 times increase in eye width was observed.

• 2011-04-01

著者

• Yamaguchi Koichi

  Renesas Electronics

• Mizuno Masayuki

  Renesas Electronics

関連論文

• A Duobinary Signaling for Asymmetric Multi-Chip Communication
• Dicode Partial Response Signaling over Inductively-Coupled Channel

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